
`timescale 1ns/1ps

module	test_vga(
	input									clk,
	input									rst_n,
	
	input[3:0]							VGA_mode,
	
	output[7:0]							VGA_R,
	output[7:0]							VGA_G,
	output[7:0]							VGA_B,
	
	output								VGA_Hsync,
	output								VGA_Vsync,
	output								VGA_Blank_n,
	output								VGA_De,
	output								VGA_CLK,
	output								Pslave_n
	);


wire[23:0]				DVI_qe;
wire					DVI_de;
wire[7:0]				Rin,Gin,Bin;
wire[7:0]				VGA_Rout;	
wire[7:0]				VGA_Gout;
wire[7:0]				VGA_Bout;

wire					VGA_Vsync_0;
wire					VGA_Hsync_0;

assign	VGA_CLK		=	clk;
assign	VGA_R			=	VGA_Rout;
assign	VGA_G			=	VGA_Gout;
assign	VGA_B			=	VGA_Bout;
assign	VGA_Blank_n		=	VGA_De;
assign	VGA_Hsync		=	VGA_Hsync_0;
assign	VGA_Vsync		=	!VGA_Vsync_0;


wire[3:0]	mode;
wire	mode_valid;

/*PLL	uPLL(
			.areset(PLL_rst),
			.inclk0(clk),
			.c0(sysclk),
			.c1(),
			.c2(),
			.locked(sysrst_n)
			);*/

//PLL uPLL(
//	.CLKI(clk), 
//	.RST(PLL_rst), 
//	.CLKOP(sysclk),
//	.CLKOS(),
//	.LOCK(sysrst_n)
//	);
			
Test_pattern uTest_pattern(
	.clk(clk),
	.rst_n(rst_n),
	
	.data_req(data_req),
	.mode_valid(1'b1),
	.mode(VGA_mode),
	
	.Rout(Rin),
	.Gout(Gin),
	.Bout(Bin)
	);	
			
		

LCD_Driver	uDisplay(
			.clk(clk),
			.rst_n(rst_n),
	
			.Rin(Rin),
			.Gin(Gin),
			.Bin(Bin),
			
			.data_req(data_req),
			.vsync(VGA_Vsync_0),
			.hsync(VGA_Hsync_0),
			.de(VGA_De),
			.Rout(VGA_Rout),
			.Gout(VGA_Gout),
			.Bout(VGA_Bout)
			);
			
endmodule
		